Method and system for the modular design and layout of integrated circuits

ABSTRACT

An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end-application, each of the modular tiles being configured to perform a predetermined function and constructed to have approximately the same length and width dimensions. The modular tiles are used to form the IC in a standard-IC fabrication process. In many implementations, the physical layout of the IC does not include the step of routing. Capabilities also include configuring the modular tiles to have programmable performance parameters and configuring the modular tiles to cooperate usefully with one another based on a programmable parameter.

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

Not applicable.

REFERENCE TO SEQUENCE LISTING, A TABLE, OR A COMPUTER LISTING APPENDIX

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COPYRIGHT NOTICE

A portion of the disclosure of this patent document contains materialthat is subject to copyright protection. The copyright owner has noobjection to the facsimile reproduction by anyone of the patent documentor patent disclosure as it appears in the Patent and Trademark Office,patent file or records, but otherwise reserves all copyright rightswhatsoever.

FIELD OF THE INVENTION

The present invention relates to the design and layout of integratedcircuits

(ICs). More specifically, the invention relates to a modular partitionapproach used to create extremely versatile high performance,application specific ICs in the shortest possible timeframe.

BACKGROUND OF THE INVENTION

An example of a traditional IC comprised of a core circuit andinput/output (I/O) terminals is illustrated by way of example in FIG. 1.The core circuit is typically comprised of several functional blocks.For example, in a multi-output power management IC (PMIC), the corecircuit could consist of several linear regulators, various switch-modeDC-DC converters, system control and sequencing circuits, supervisorycircuits, etc. Typically, each of the functional blocks in the corecircuit has terminals that are routed to the bond pads, located aroundthe perimeter of the IC, which are connected to package pins throughwire bonds, as shown by way of example in FIG. 2. Alternatively,Chip-Scale Packaging (CSP) may be used, where a top metal RedistributionLayer (RDL) is used to reposition the I/O terminal locations, and solderbumps or balls are placed on the redistributed I/O pads such that the ICcan be flipped over and mounted on a chip carrier laminate substrate.This packaging process is commonly referred to as “flip-chip”technology.

In particular, FIG. 1 shows an example of a traditional IC comprised ofa core circuit 101 and I/O terminals 105, and FIG. 2 shows the IC withbond wires 205 connecting bond pads 120 of the IC to package leads 210,which get soldered to a conventional PCB (not shown) according to knowntechniques. Core circuit 101 is typically comprised of severalfunctional blocks 115. For example, without limitation, in amulti-output PMIC, the core circuit may comprise several linearregulators, various switch-mode DC-DC converters, system control andsequencing circuits, supervisory circuits, etc. Typically, eachfunctional block 115 in core circuit 101 has terminals that are routedto bond pads 120, located around the perimeter of the IC, which areconnected to package pins 210 through wire bonds 205, as shown by way ofexample in FIG. 2. This assembly suffers from parasitics associated withthe internal routing from functional blocks 115 in core circuit 101 toI/O terminals 105 and from I/O terminals 105 to the PCB through wirebonds 205 and package leads 210.

Unfortunately, the prior art suffers from parasitic resistance,capacitance, and inductance (parasitics) associated with the internal ICinterconnections from the functional blocks in the core to the I/O pads,and from the parasitics related to the wire bonds and package pins, inthe case of traditional wire bond type packages. Furthermore, theassembly of the IC in a package with wire bonds and pins unnecessarilywastes space, which is critical in certain space limited applications.In the case of flip-chip CSP, the prior art also suffers from the RDLrouting parasitics.

Furthermore, prior art approaches lack the ability to be easilyreconfigured or rearranged to create new products or derivativeproducts. For example, adding new functional blocks would require acomplete re-layout of the IC in order to fit-in the additionalcircuitry. Conversely, removing functional blocks is achieved either bykeeping the circuitry on the IC and disabling it or deleting thecircuitry. In the former case the die size and cost is not optimal,while in the latter case, the IC re-layout time requires additionalresearch and development time and resources, which are very expensive.In both cases, adding or subtracting circuitry to modify existingproducts or create new ones, adds risk and cost.

In view of the foregoing there is a need for an improved method fordeveloping highly integrated PMICs that reduces unwanted IC-to-PCB(printed circuit board) parasitics, lowers development risk, and allowsmuch shorter IC and system development times compared to previoussolutions.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example, and not by wayof limitation, in the figures of the accompanying drawings and in whichlike reference numerals refer to similar elements and in which:

FIG. 1 and FIG. 2 illustrate examples of traditional IC layout. FIG. 1shows an example of a traditional IC comprised of a core circuit and I/Oterminals, and FIG. 2 shows the IC with wire bonds connecting the I/Oterminals of the IC to package pins soldered to a printed circuit board(PCB);

FIG. 3 a illustrates a typical layout of an exemplary modular tileconstruct, which includes functional circuitry and embedded I/Oterminals suitably arranged for Chip Scale Packaging (CSP), inaccordance with an embodiment of the present invention, and FIG. 3 billustrates several alternate embodiments of some of the core regulatortiles typically required to form a PMIC, in accordance with anembodiment of the present invention;

FIG. 4 illustrates an exemplary modular PMIC comprised of fixed sizetiles with embedded I/O terminals, memory, interface circuitry and astandard signal bus which connects the tiles in accordance with anembodiment of the present invention;

FIGS. 5 a and 5 b show exemplary programmable General Purpose I/Os(GPIO) that drive white LED backlights with programmable brightness anddimming control, in accordance with embodiments of the presentinvention. FIG. 5 a shows a programmable GPIO with a current-regulatedoutput, and FIG. 5 b shows a programmable GPIO with a pulse widthmodulated (PWM) current-regulated output;

FIGS. 6 a and 6 b illustrate two examples of power-up tracking,coincident and ratiometric, in accordance with embodiments of thepresent invention. FIG. 6 a shows ratiometric tracking, and FIG. 6 bshows coincident tracking;

FIGS. 7 a and 7 b show exemplary parallel regulator tile arrangements toextend output drive and increase output power, in accordance withembodiments of the present invention;

FIGS. 8 a, 8 b, and 8 c illustrate exemplary two-tile connectionarrangements, in accordance with an embodiment of the present invention;and

FIG. 9 illustrates an exemplary method for developing a PMIC accordingto the preferred embodiment of the present invention.

FIGS. 10 a and 10 b illustrate exemplary modular IC layouts with I/Oterminals repositioned within tiles or re-located in other tiles orredistributed outside of the tiles and placed around the perimeter ofthe IC, in accordance with an embodiment of the present invention.

Unless otherwise indicated illustrations in the figures are notnecessarily drawn to scale.

SUMMARY OF THE INVENTION

To achieve the forgoing and other objects and in accordance with thepurpose of the invention, a variety of techniques for the modular designand layout of integrated circuits are described.

A method of constructing integrated circuits (IC) is provided thatinclude the steps of specifying a plurality of required tile modulessuitable for a particular end-application, each of the modular tilesbeing configured to perform a predetermined function and furtherconstructed to have approximately the same length and width dimensions.The tile modules are used to specify and form the IC in a standard ICfabrication process, which may also include the step of embedding I/Oterminals and/or bond pads into a surface of at least some of themodular tiles. In the preferred embodiment, the physical layout of theIC does not include the step of routing.

In alternate embodiments, any combination of the followings steps may befurther included: configuring at least one of the modular tiles to haveat least one programmable performance parameter, the programmabilitybeing functional at least after forming the IC; configuring a pluralityof the modular tiles to cooperate, usefully with one another based on aprogrammable parameter, the programmability being functional at leastafter forming the IC and operable to reconfigure the cooperating modulartile plurality to a desired cooperating configuration.

Steps for implementing any of the foregoing functions are also provided.In yet other embodiments, an IC is provided, which includes an IC dieformed to include a plurality of modular tiles in its active layer, eachof the modular tiles being configured to perform a predeterminedfunction and further configured to have approximately the same lengthand width dimensions, and exposed input/output (I/O) terminals embeddedin the active layer, the I/O terminals being in electrical communicationwith corresponding circuit elements of the modular tile plurality andoperable to join with solder balls or bumps used in mounting andfunctionally connecting the IC with a printed circuit board (PCB). Someembodiments are configured such that each of the modular tiles isconfigured with a standardized set of connectors that communicativelyinterconnect the modular tiles, wherein at least a portion of thestandardized inter-connectors comprised by each modular tile aredisposed-at approximately fixed locations in or on the modular tile tothereby facilitate the alignment and interconnection betweencorresponding standardized inter-connectors of adjacent modular tiles.Other embodiments further include interfacing circuitry configured intoat least one of the tiles, the interface circuitry being operable toproperly interface the at least one interface configured tile to thestandardized inter-connectors. Yet other embodiments are configured suchthat at least one of the modular tiles further comprises a memorystorage device, which, for example, can be volatile or non-volatilememory that controls functions or characteristics of its associatedtile.

In alternate embodiments of the present invention, any combination ofthe following components/features may be further included: a top metalredistribution layer (RDL) configured to re-route the I/O terminals todifferent locations within a given modular tile or to one or more othermodular tile(s), to thereby enable a plurality of alternative IC packagepinouts based on the IC die or to accommodate conventional IC packagetypes; a wafer-level, chip scale package (CSP) that is configured tosuitably package the IC die to be thereby operable for direct functionaljoining to the PCB, in which the IC device does not include an I/Oredistribution routing or an intermediate chip carrier; at least onemodular tile functioning as a linear regulator, a switch-mode DC-DCconverter, a charge pump, a battery charger, a monitoring circuit, ameasurement circuit, a supervisory function, or a control and sequencingcircuit; at least one of the modular tiles is configured to have atleast one programmable performance parameter, feature, and/or function;at least one of the modular tiles is a power supply regulator, and theat least one performance parameter is an input/output current/voltageelectrical characteristic, a start-up profile characteristic, asteady-state operation characteristic, a dynamic transient responsecharacteristic, a fault condition handling characteristic, or a shutdowncharacteristics of the regulator; an inter-tile master controller unitoperable for selectively interconnecting inputs and/or outputs of themodular tiles to cooperate usefully with one another based on aprogrammable parameter, the programmability being operable toreconfigure the cooperating modular tile plurality into a desiredcooperating configuration; in which the IC device includes modular tileshaving a plurality of output signals, and in which the master controllerunit is configured to control the power-up characteristic (e.g.; turn-ontime, ramp-up rate, or the tracking of one output to another) and/orshutdown characteristic of at least some of the cooperating modular tileplurality; in which the master controller is configured to furtherindividually control at least one start-up characteristic (e.g.,start-up sequence order and timing, or ramp rate and tracking details)of at least some of the cooperating modular tile plurality.

In yet other embodiments of the present invention, at least one of saidexposed terminals is embedded in or with the modular tiles or a similargeometric construct, and in some embodiments none of the exposedterminals are embedded in said modular tiles or a similar geometricconstruct.

Other features, advantages, and object of the present invention willbecome more apparent and be more readily understood from the followingdetailed description, which should be read in conjunction with theaccompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention is best understood by reference to the detailedfigures and description set forth herein.

Embodiments of the invention are discussed below with reference to theFigures. However, those skilled in the art will readily appreciate thatthe detailed description given herein with respect to these figures isfor explanatory purposes as the invention extends beyond these limitedembodiments. For example, it should be appreciated that those skilled inthe art will, in light of the teachings of the present invention,recognize a multiplicity of alternate and suitable approaches, dependingupon the needs of the particular application, to implement thefunctionality of any given detail described herein, beyond theparticular implementation choices in the following embodiments describedand shown. That is, there are numerous modifications and variations ofthe invention that are too numerous to be listed but that all fit withinthe scope of the invention. Also, singular words should be read asplural and vice versa and masculine as feminine and vice versa, whereappropriate, and alternatives embodiments do not necessarily imply thatthe two are mutually exclusive.

The present invention will now be described in detail with reference toembodiments thereof as illustrated in the accompanying drawings.

Some embodiments of the present invention may be particularly useful fordeveloping highly integrated PMICs. These embodiments create a modularpartition integrated circuit comprised of an array of programmabletiles, which include, without limitation, functional circuit blocks aswell as I/O terminals that connect directly to a PCB. Embodiments of thepresent invention provide a smaller overall solution, reduce unwantedIC-to-PCB parasitics, lower development risk, and allow much shorter ICand system development times compared to conventional solutions.

FIG. 3 illustrates an array of exemplary modular tile constructs for anIC, in accordance with an embodiment of the present invention. Thepresent embodiment utilizes a modular partition approach forconstructing ICs, which generally minimizes product development risk,improves new product time-to-market, reduces overall IC and end-systemsolution size, and generally eliminates unwanted parasitics. In thefollowing description “module” refers to a function block, for example,without limitation, a low drop out (LDO) regulator, a DC-DC converter, aportion of a buck-boost converter, a battery charger, ananalog-to-digital converter, a digital-to-analog converter, amicro-controller, a real-time-clock, general purpose input/outputcircuits, etc, and “tile” refers to a group of one or more modules. FIG.3 a illustrates a typical layout of an exemplary modular tile construct,which includes functional circuitry and embedded I/O terminals suitablyarranged for Chip Scale Packaging (CSP), in accordance with anembodiment of the present invention. FIG. 3 b illustrates severalalternate embodiments of some of the core regulator tiles typicallyrequired to form a PMIC, in accordance with an embodiment of the presentinvention. The exemplary tiles shown in FIG. 3 b include various formsof Switching DC-DC Converter tiles, LDO tiles, Battery Charger tiles andGPIO tiles. In FIG. 3 a, the tiles 301 comprise both functional circuitblock(s) 305 and embedded I/O terminals 310. The representative tilesshown in FIG. 3 b are just a few examples of tiles that could be usefulfor forming PMICs. Those skilled in the art, in light of the teachingsof the present invention, will readily recognize that many other tilesand terminal configurations can be created within the spirit and scopeof the present invention to form multiplicity of PMIC products thataddress the needs of a broad range of end applications. Various tilessimilar to tile 301 shown by way of example in FIG. 3 can be constructedand arranged in an array to form a complete PMIC as shown by way ofexample in FIG. 4.

FIG. 4 illustrates an exemplary modular PMIC comprised of fixed sizetiles 301 with embedded I/O terminals 310, memory 410, interfacecircuitry 420, and a standard signal bus 430, which connects the tiles,in accordance with an embodiment of the present invention. In thepreferred embodiment of the present invention, standard signal bus 430is a standardized set of connectors that communicatively interconnecttiles 301 and comprise dedicated signal lines, communication signallines, control signal lines, and power supply and ground buses, and inwhich the portion of standard signal bus 430 comprised in each tile 301is disposed at approximately fixed locations to thereby facilitate thealignment and interconnection between corresponding standard signalbuses 430 of adjacent modular tiles.

In the preferred embodiment of the present invention, the modular tilearray-based PMIC is packaged in a wafer-level CSP, which can be attacheddirectly to a PCB without I/O redistribution or intermediate chipcarrier. Wafer-level chip scale packaging allows solder balls or bumpsto be placed directly on I/O terminals 310, which are embedded in tiles301. This method generally eliminates much, if not all, of the unwantedparasitics and wasted area found in the prior art, which results fromthe large physical separation between the functional circuit block inthe IC core and the package pins. In some embodiments, optionalre-distribution (interconnect) layers may be used to re-route I/Oterminals 310 to different locations on tile 301 or across tiles 301 toother locations on the IC to allow for various CSP pinouts with the samedie or to accommodate conventional wire bond or BGA type packaging, ifrequired by the end user. Other suitable packages include, but are notlimited to, SOIC, SSOP, TSSOP, QSOP, MSOP, MLF/QFN, LQFP, MQFP, TQFP,PLCC, MCP, PDIP. As those skilled in the art will appreciate, and asdescribed above, for these leaded packages, the I/O pads need to beredistributed in order to wire bond out to the package leads (see FIGS.10 a and 10 b for other exemplary layouts of a modular IC with I/Oterminals re-positioned within tiles and/or re-located in other tiles orre-distributed outside of the tiles and placed around the perimeter ofthe modular IC).

Another aspect of the foregoing modular partition approach is that tiles301 can be rearranged very easily and quickly to provide a multiplicityof alternative combinations of functions and pinouts depending upon theparticular end-system application desired. Given that I/O terminals 310are embedded into tiles 301, the risk of performance degradation, due tonuisance parasitics and parasitic signal coupling, associated withreplacing and rerouting I/O signals from the core to peripheral I/Oterminals 310 is significantly reduced to acceptable levels, if notgenerally eliminated. In the preferred embodiment of the presentinvention, tiles 301 are fixed size or approximately fixed size, forexample, without limitation, multiples of 0.5 mm on a side (e.g.,0.5×0.5 mm, 0.5×1 mm, 1×1 mm, 1×1.5 mm, 1×2 mm, etc.) with fixedplacement of I/O terminals 310 on a 0.5 mm grid, as shown by way ofexample in FIG. 3. The tiles can be implemented in any suitable rotationor flipped along the vertical or horizontal axis to accommodate allconventional IC layout configurations. In addition, a portion of thetiles attributes or design details can be customized when the IC isconstructed.

In some practical embodiments of the present invention, the tiles mayinclude standard power supply and control signal buses, which enablesthe tiles to be automatically placed and connected together, whereby thetiles link-up to form an integrated, scalable power supply grid andcontrol/communication interconnect network, an example of which isillustrated in FIG. 4. It should be appreciated that this is somewhatanalogous to power buses on digital standard cells that enable thestandard cells to be placed automatically and the power supply busesextend continuously across a row of standard cell logic. Somecontemplated control, communication, and power supply signals include,but are not limited to: (a) “committed”, fixed-purpose signals such as,without limitation, voltage references and voltage sources, currentreferences and current sources, oscillator signals, clock timing andsynchronization signals, data and address signals for programming andcommunication, analog or digital electrical trimming signals, variousground signals including analog ground, digital ground, and signalground sense, various power supply signals including analog core powersupply, digital core power supply, I/O power supply, and Non-VolatileMemory (NVM) programming power supply, as well as (b) “uncommitted”analog and/or digital signals, which can be claimed by one or moremodules for inter-tile connections, control, and/or communication. Insome embodiments of the present invention, at least one of the modulartiles is configured to control an electrical and/or performancecharacteristic at least in part based on information stored in itsassociated memory 410. In some other embodiments of the presentinvention, at least one of the modular tiles is configured to generate avoltage reference and/or clock signal(s) that are operable for use by atleast of the other modular tiles.

In the preferred embodiment of the present invention, the tiles containstandard interface circuitry 420 as shown by way of example in FIG. 4,which allows the connection and level-shifting of the standard control,communication, and power supply signals. Each tile contains multiplex(mux) and de-multiplex (demux) interface circuitry and encoders anddecoders which can be programmed to connect either “committed” or“uncommitted” signals from tile-to-tile. In the preferred embodiment ofthe present invention, 16 “uncommitted” signal lines are available foreach tile to mux-in or mux-out control signals. For example, one tilecan mux-out a power good signal to one of the “uncommitted” andunclaimed signal lines and another tile can mux-in this signal tocontrol power up sequencing. Those skilled in the art will recognizemany potential uses for the “uncommitted” signal lines and interfacemuxes within each tile. Level-shift circuits are also included in thetile's interface circuitry to allow mixed power supply operation andensure proper communication between tiles that use different powersupplies. By including in each tile a standard bus offixed-purpose/fixed-location signals for communication and control, andpower supply and ground, along with appropriate interface circuitry forconnecting, muxing/de-muxing, and level-shifting these signals, tilescan be relatively easily arranged and readily rearranged to form optimalapplication specific PMICs depending upon the needs of the particularend application. In the preferred embodiment of the present invention,“plug-and-play” tiles, as described above, with approximately fixed sizeand standard inter-connect signals and interface circuitry are createdto allow rapid development of PMICs. A comprehensive library of modulesand tiles, including, without limitation, linear regulators, switch-modeDC-DC converters, charge pumps, battery chargers, monitoring circuits,measurement circuits, supervisory functions, control and sequencingcircuits, etc., may be developed and continuously improved such thatvarious application specific PMICs may be produced in a significantlyshorter timeframe than what has been accomplished using the traditionalfull-custom design and layout approach. New PMIC products may bedeveloped from the ground up, from specification-to-silicon, in daysinstead of months, as is presently achievable with the prior artsolution.

In order to develop and produce PMICs quickly according to the presentembodiment, tiles 301 are a standard size with standard signals andinterface circuitry, as described above, and are programmable to allowreconfiguration for many different end-applications. For example,without limitation, the output voltages and currents of power supplyregulator modules are programmable. In the preferred embodiment, otherfunctions such as, but not limited to, the start-up profile,steady-state operation, dynamic transient response, fault conditionhandling, and shutdown characteristics of the regulator are alsoprogrammable to allow performance optimization for various applications.

In the preferred embodiment of the present invention, each tile includesassociated memory 410 as shown by way of example in FIG. 4, which can beprogrammed by an external microprocessor via the PMIC's Master ControlTile. The tile memory of the present embodiment may be realized by anysuitable memory technology that best suits the needs of the particularPMIC end application, some common examples of which include, but are notlimited to, various forms of either volatile or Non-Volatile Memory(NVM) or a combination of both types. The Master Control Tile of thepresent embodiment comprises interface logic, which is at leastconfigured to convey the host microprocessor communication and commandsto the tiles. Each tile preferably has a certain memory allocation withone or more unique addresses, which are addressable by the hostmicroprocessor via the Master Control Tile interface logic. An aspect ofthe addressable memory in the tile(s) of the present embodiment is thateach bit or byte of memory preferably has a unique address; otherwise itis contemplated that there will be conflicts in many practicalapplications, which is often a general rule of writing and reading anytype of memory in a typical system. When multiple tiles are configuredtogether, the memory of the present embodiment is distributed throughoutthe IC within the tiles as opposed to the traditional approach ofconsolidating all of the memory in a central location in the IC. Anotheraspect of the present distributed tile memory approach is that itenables scalability and flexibility (e.g., adding tiles, removing tiles,and rearranging tiles is relatively easy) without requiring timeconsuming custom re-layout of the memory, and memory interface andcontrol logic. In one embodiment of the present invention, described byway of example and not limitation, 32 bits of memory are incorporated ineach tile and segmented into four 8-bit configuration bytes, for whichthe following exemplary description is based upon. The Master ControlTile utilizes a multiplexed address/data communication bus wherein thesame 8 signal lines are used for both addressing and data transfer in atwo-phase communication sequence. During the first phase ofcommunication between the master tile and target tile, the master placesan 8-bit address on the communication bus, which identifies the targettile and selects the memory byte within the tile. In the second phase,the data byte is written to or read from the target tile using the same8-line communication bus.

By incorporating memory in each tile the aforementioned distributedmemory architecture can achieve superior performance in many practicalapplications whereas conventional methods suffer from the inefficienciescaused by their consolidation of most, if not all, of the PMIC memorywithin a central location. Thus, the present embodiment provides anextremely versatile and scalable PMIC architecture, which enables tilesto be readily added, subtracted, repositioned, and/or rearranged withoutdisrupting the flow of information and communication from the hostmicroprocessor to the target tile(s). Furthermore, in accordance withanother aspect of in the present invention, as PMIC functionality isscaled up or down to meet various end-system application requirements,time consuming custom re-layout and reconnection is avoided at leastbecause the memory and memory interface is incorporated in the tiles,and the standard inter-connect bus described above ensures properconnection and signal integrity. In the preferred embodiment, theprogrammed parameters can be stored in NVM (Non-Volatile Memory), whichis contemplated to be various forms including various forms of OTP (OneTime Programming) or EPROM, or EEPROM, or FLASH memory.

An aspect of this programmable parameter capability is to effectivelysimplify the planning and inventory control for both the IC supplier andits customer, at least because one product can satisfy manyapplications, without significantly compromising product performance orcost. In many applications of the present invention, fastertime-to-market is achieved for both the IC supplier and its customers,because the same IC can be reconfigured via software programming tosatisfy different end systems requirements. In addition, there are alsomaterial cost savings provided by the present invention in manypractical applications, at least because the cost to produce extra masksets to create multiple product options is avoided. Additionalefficiencies are enabled by the present capability of programmingvarious parameters, including, without limitation, output voltagesand/or currents, dynamic transient response, start-up characteristics,and shutdown behavior. In some embodiments, a mixture of non-volatileand volatile memory is included in some or all of the tiles to enablefixed functionality and/or dynamic programming “on-the-fly” operation.

A particularly useful example of the application of programmablefunctionality is General purpose I/O (GPIO) circuits, which providesupervisory and control functions. GPIOs include, without limitation,digital inputs and outputs, as well as analog inputs and outputs.Digital input/output functions include, but are not limited to, standardlogic functions and drivers, which are well known to those skilled inthe art. Analog inputs include, but are not limited to, voltage,current, time, frequency, temperature, pressure, etc. Analog GPIO inputsignal processing functions include, but are not limited to, buffering,amplifying, or attenuating single-ended or differential analog inputs,which can then be compared, measured, converted, or used for control.Analog output functions include, but are not limited to, voltage,current, time, and frequency references and sources. For example,without limitation, a GPIO may be programmed to provide an outputcurrent source to drive white LED backlights with programmable PWMdimming, as depicted by way of example in FIGS. 5 a and 5 b.

FIGS. 5 a and 5 b show exemplary programmable GPIOs that drive white LEDbacklights with programmable brightness and dimming control, inaccordance with embodiments of the present invention. FIG. 5 a shows aprogrammable GPIO with a current-regulated output, and FIG. 5 b shows aprogrammable GPIO with a PWM current-regulated output. In the embodimentshown in FIG. 5 a, an amplifier A1 is supplied with a programmablereference REFGEN that is used to regulate the output current. In theembodiment shown in FIG. 5 b, output current is regulated by anamplifier A2 and switched on and off by a pulse width modulator PWMGENthat provides a programmable PWM frequency and duty cycle. Those skilledin the art, in light of the present teachings, will readily recognizehow to adapt almost any analog/digital functional block to be a standardprogrammable module according to the teachings of the present invention.

By way of further example, FIGS. 6 a and 6 b illustrate two examples ofprogrammable power-up tracking, coincident and ratiometric, inaccordance with embodiments of the present invention. FIG. 6 a showsratiometric tracking, and FIG. 6 b shows coincident tracking. Inratiometric tracking, all outputs finish, or settle to their finalregulated output value, at the same time, t_(F), however, the outputvoltages rise at different rates. In coincident tracking, all of theoutputs rise at the same rate, but they finish at different times. Forembodiments comprising multi-output PMICs, a master controller module ortile may manage power-up sequencing and shutdown control of all modulesand tiles. For power-up, the master controller may be programmed tocontrol functions such as, but not limited to, the turn-on time, ramp-uprate, and whether or not a particular output should track another outputas it powers up. The master controller may control start-up for example,without limitation, by utilizing a start-up sequence list, which isprogrammed with the sequence order and timing, as well as ramp rates andtracking details, for each PMIC output. This scheme makes use of thefact that each power supply module and tile has a unique address and isprogrammable. The aforementioned start-up sequencing scheme introducesthe idea of modules and tiles communicating with a master controller aswell as other modules and tiles.

Another aspect of the preferred embodiment of the present invention isease of scalability. Scalability can be classified into at least twocategories: expanding the capabilities of the PMIC by adding functions,features, inputs, and outputs, and extending the range or drive strengthof the PMIC outputs by paralleling modules. In the former case, thefixed size and programmability of tiles according to the preferredembodiment of the present invention enables relatively easy “drop-in”,add-on functions. In the latter case, module outputs could be connectedin parallel to provide increased power supply output capability. Anapproach known to those skilled in the art to increase output powercapability of a DC-DC converter is to combine outputs by summing eachswitching stage or phase through their respective inductors as shownby-way of example in FIG. 7 a. This technique will be recognized bythose skilled in the art as multi-phase or poly-phase DC-DC converters.Regulator outputs could also be summed in single-phase switchingregulators, as shown by way of example in FIG. 7 b, or in a linearregulator to extend the output power range. In both linear and switchingregulators the module's power supply controllers could easily beprogrammed and configured for parallel or multi-phase operation.Likewise, module outputs could be cascaded or connected in series, whereone module output becomes the input supply to another module, as shownby way of example in FIG. 8. Depending up on the needs of the particularapplication, those skilled in the art will readily recognize amultiplicity of alternative and suitable dynamically configurablearchitectures that can be realized without having to rework the layoutof the IC or perform design validation, circuit simulations, or physicaldesign verification.

FIGS. 7 a and 7 b show exemplary parallel regulator tile arrangements toextend output drive and increase output power, in accordance withembodiments of the present invention. The arrangement shown in FIG. 7 ahas a multi-phase output comprised of two buck tiles 701 and 702configured and arranged to provide two times the output current. In thepresent embodiment, tile 701 and tile 702 are programmed to share outputcurrent and to run out-of-phase through inductors L1 and L2 to reduceinput ripple and input bypass capacitance. The arrangement shown in FIG.7 b comprises single-phase buck stages to provide two times the outputcurrent. In this embodiment a tile 703 and a tile 704 are programmed toswitch in-phase with a single inductor L3. In the preferred embodimentof FIGS. 7 a and 7 b the buck tiles are configured and controlled by amaster tile (not shown), and the tiles can communicate with masterand/or each other, thereby enabling a significantly higher level ofperformance.

FIG. 8 illustrates exemplary tile-to-tile connection arrangements, inaccordance with an embodiment of the present invention. In the presentembodiment, the output of a regulator tile 801 feeds the input of aregulator tile 802. In the example of FIG. 8 a, both tiles are buckswitching regulators, while in FIG. 8 b a buck switching regulator tile,803, output supplies the input of a LDO or linear regulator tile 804 andin FIG. 8 c two general-purpose switching regulator tiles 805 and 806are connected to form a buck-boost power supply. Various tile-to-tilearrangements can be readily implemented to provide efficient powermanagement circuits. In the example shown in FIG. 8 b, the output of aswitching regulator tile can feed the input of a linear battery chargertile to achieve more efficient battery charging in power-limitedapplications. An example of common power-limited applications, withoutlimitation, are USB fed battery chargers applications, which typicallyhave limited input supply current of 100 mA or 500 mA. The chargingcurrent provided by a linear battery charger is equal to the inputsupply current. However, if the linear charging regulator is fed with aswitching regulator whose input is connected to the USB source and whoseoutput voltage is regulated to V_(BST)+100 mV (for example, assuming thetotal combined dropout voltage of the switching regulator and linearcharger is 100 mV), then the charging current isI_(CHRG)=η*V_(IN)·Iin/V_(BAT), where η is the efficiency. The typicalefficiency of commonly available synchronous switching regulators forthis type of application is 90%. Therefore, the battery charging currentfor a 5V, 100 mA USB input and a 3V discharged lithium battery isI_(CHRG)=0.9*5V·100 mA/3.1V=145 mA. As the battery voltage approachesthe input voltage the benefit of the more efficient switching regulatorbecomes less advantageous.

Other useful applications of interconnected tiles includes, withoutlimitation, the formation of a buck-boost switching regulator, as shownby way of example in FIG. 8c. As shown, two general-purpose switchingtiles could be configured and connected to realize a buck-boost powersupply, which regulates an output voltage that can be either greaterthan or less than the input supply voltage. For example, withoutlimitation, in many lithium battery powered portable electronicsapplications a regulated 3.3V power supply is required to power thesystem's I/O circuitry. However, the lithium battery voltage cantypically vary from 4.2V when it is fully charged to 3V or less when itis discharged. Therefore, a power conversion circuit is needed that canbuck-down and boost-up the output voltage from the input supply. Thoseskilled in the art will readily recognize that this can be achievedaccording to the teachings of the present invention by configuring andconnecting two general-purpose, programmable switching regulator tilesand controlling their switching operation based on the input batteryvoltage and sensed output voltage. This flexibility allows the samephysical IC to have some of its terminals externally configured into onebuck-boost converter or two separate DC-DC converters.

In the preferred embodiment, the combination of standard-size tiles,programmable functionality and electrical characteristics enables highlyintegrated, application specific PMICs to be developed quickly. In manypractical situations, PMIC development times using an approach accordingto the preferred embodiment of the present invention can be measured inhours instead of weeks. With a comprehensive tile library comprisingproduction ready, proven designs, PMICs may be put together without theneed for traditional design validation for example, without limitation,no circuit simulation or DRC/LVS physical design verification. It shouldbe clear that the foregoing embodiments provide a substantiallydifferent approach from the prior art (e.g., analog/digital standard IPlibraries, etc.) at least in that tiles of the preferred embodiment arefixed size or approximately fixed size, programmable analog/mixed-signaltiles, and the tile dimensions and ports are optimized to enable thesmallest solution size and fastest time-to-market. For example, in oneimplementation instance of the preferred embodiment, all of the tiles'length and width dimensions are multiples of approximately 0.5 mm with0.5 mm I/O terminal pitch, as shown in FIG. 4, with a standard power,communication, and control buses, which automatically link up when thetiles are placed together. In this way, it is possible to very rapidlyand easily put together a highly integrated Power Management IC, atleast because the tile library is already set up with these efficienciesin mind.

FIG. 9 illustrates an exemplary method for developing a PMIC accordingto the preferred embodiment of the present invention. The processincludes the following steps, in an exemplary sequence beginning with aStep 910 for specifying the list of required modules for the particularend-application, then a Step 920 of determining the preferred PMICpinout and end-application PCB layout, placing the tiles to form thePMIC, and a Step 930 of generating the chip data for mask reticles forwafer fabrication. Of course, these steps may be performed in anysuitable order and other steps may be introduced at any point, dependingupon the needs of the particular implementation. The actual physicallayout of the PMIC involves, without limitation, placing tiles, similarto the conventional process of digital cell place and route layout,which is used for logic block design, except in this method there is noneed for routing, at least because each tile includes a standard powersupply and control signal bus and circuitry which automatically linksthe tiles together. By reusing proven tiles, the development risk of thePMIC and end-application is substantially reduced, enabling significanttime-to-market advantages for both the PMIC supplier and end-systemmanufacturer. Furthermore, by making the modules highly programmable andreconfigurable, the end-system manufacturer can specify one PMIC thatcould be used in many end-system models, which further reduces risk andsimplifies planning and inventory control.

FIGS. 10 a and 10 b illustrate exemplary modular IC layouts with I/Oterminals repositioned within tiles or relocated in other tiles orredistributed outside of the tiles and placed around the perimeter ofthe IC, in accordance with an embodiment of the present invention. FIG.10 a exemplifies a modular integrated circuit with terminals or I/O padsrepositioned within tiles or relocated in other tiles and FIG. 10 bexemplifies a modular integrated circuit where the terminals or I/O padsare configured outside the tiles or located around perimeter of modularIC. Depending upon the needs of the particular application, thoseskilled in the art, in light of the present invention, will readilyrecognize a multiplicity of alternative and suitable approaches tolocate, configure, and connect terminals or I/O pads including varioushybrid combinations of the embodiments shown.

Having fully described at least one embodiment of the present invention,other equivalent or alternative means for implementing a modularpartition approach to quickly create versatile, high performance,application specific ICs according to the present invention will beapparent to those skilled in the art. The invention has been describedabove by way of illustration, and the specific embodiments disclosed arenot intended to limit the invention to the particular forms disclosed.The invention is thus to cover all modifications, equivalents, andalternatives falling within the spirit and scope of the followingclaims.

1. A method of constructing integrated circuits (IC), the methodcomprising the Steps of: specifying a plurality of required modulartiles or similar geometric construct suitable for a particularend-application, each of said modular tiles or similar geometricconstruct being configured to perform a predetermined function andfurther configured to have approximately the same length and widthdimensions, or multiples of approximately fixed and/or fixed unit lengthand/or width dimensions; generating a physical layout for the IC usingsaid modular tiles or similar geometric construct in any rotation ormirror image; generating chip data corresponding to said modular tile IClayout; generating mask reticles corresponding to said chip data; andforming the IC on a wafer based on said mask reticles.
 2. The method ofclaim 1, further comprising the step of embedding terminals and/or bondpads into a surface of at least some of said modular tiles.
 3. Themethod of claim 1, in which said physical layout Step does not comprisethe step of routing or layout editing to connect signals.
 4. The methodof claim 1, further comprising the Step of validating that said at leastone modular tile meets certain performance specification(s) required bysaid end-application, thereby enabling the reuse of proven modulartiles.
 5. The method of claim 1, further comprising the Step ofconfiguring at least one of said modular tiles to have at least oneprogrammable performance parameter, said programmability beingfunctional at least after forming the IC.
 6. The method of claim 5, inwhich at least one of said modular tiles is a power supply, and said atleast one performance parameter is an input/output current/voltageelectrical characteristic.
 7. The method of claim 1, further comprisingthe Step of configuring a plurality of said modular tiles to cooperateusefully with one another based on a programmable parameter, saidprogrammability being functional at least after forming the IC andoperable to reconfigure said cooperating modular tile plurality to adesired cooperating configuration.
 8. A modular integrated circuit (IC)device formed of tiles or similar geometric construct, the IC devicecomprising: an IC die formed to include a plurality of modular tiles orsimilar geometric constructs, each of said modular tiles or similargeometric constructs being configured to perform a predeterminedfunction and further configured to have approximately the same lengthand width dimensions; or multiples of approximately fixed and/or fixedunit length and/or width dimensions in any rotation or mirror image; andexposed terminals, said terminals being in electrical communication withcorresponding circuit elements of said modular tile plurality.
 9. The ICdevice of claim 8, further comprising redistribution layer(s) tore-route said terminals to different locations within a given modulartile, and/or to locations within one or more other modular tile(s),and/or to locations outside of any modular tile to thereby enable aplurality of alternative IC package pinouts based on said IC die or toaccommodate conventional IC package types.
 10. The IC device of claim 8,further comprising a wafer-level, chip scale package (CSP) that isconfigured to suitably package said IC die to be thereby operable fordirect functional joining to said PCB, said IC device not comprisingterminal redistribution routing layer(s) or intermediate chip carrier.11. The IC device of claim 8, in which at least one of said modulartiles is pre-validated to achieve certain performance requirement(s)required by an end-application, said at least one validated modular tilebeing selected from a library of validated modular, tiles, therebyenabling the reuse of proven modular tiles in said IC device.
 12. The ICdevice of claim 11, in which said library comprises at least onevalidated modular tile functioning as a linear regulator, a switch-modeDC-DC converter, a charge pump, a battery charger, a monitoring circuit,a measurement circuit, a supervisory function, or a control andsequencing circuit.
 13. The IC device of claim 8, in which at least oneof said modular tiles is configured to have at least one programmableperformance parameter, feature, and/or function.
 14. The IC device ofclaim 13, in which at least one of said modular tiles is a power supplyregulator, and said at least one performance parameter is aninput/output current/voltage electrical characteristic, a start-upprofile characteristic, a steady-state operation characteristic, adynamic transient response characteristic, a fault condition handlingcharacteristic, or a shutdown characteristics of the regulator.
 15. TheIC device of claim 13, in which said programmable performance parameteris stored in memory.
 16. The IC device of claim 8, further comprising aninter-tile master controller unit that is configured to be operable forconfiguring and/or controlling said modular tiles to cooperate usefullywith one another based on a programmable parameter, said programmabilitybeing operable to reconfigure said cooperating modular tile pluralityinto a desired cooperating configuration.
 17. The IC device of claim 16,in which said IC device comprises modular tiles having one or moreoutput signals, and in which said master controller unit is configuredto control the power-up characteristic and/or shutdown characteristic ofat least some of said cooperating modular tile plurality.
 18. The ICdevice of claim 17, in which said power-up control characteristiccomprises controlling the turn-on time, or ramp-up rate, or the trackingof one output to another.
 19. The IC device of claim 17, in which saidmaster controller is configured to further individually control at leastone start-up characteristic of at least some of said cooperating modulartile plurality.
 20. The IC device of claim 19, in which said start-upcharacteristic is a start-up sequence order and timing, or ramp rateand/or tracking details.
 21. The IC device of claim 16, in which atleast some of said cooperating modular tile plurality are configured tobe uniquely addressable and controllable by said master controller unit.22. The IC device of claim 8, in which at least one of said modulartiles is configured to comprise a voltage or current regulator.
 23. TheIC device of claim 8, in which said terminals are disposed in anapproximately fixed terminal grid, or pitch, to thereby enable “drop-in”placement of tiles with no additional routing or layout editing requiredto complete said IC.
 24. The IC device of claim 8, in which circuitryand/or terminals of at least two of said modular tiles are configured inseries or parallel.
 25. The IC device of claim 8, further comprising astandardized set of connectors that communicatively interconnect saidmodular tiles, wherein at least a portion of said standardizedinter-connectors comprised by each modular tile are disposed atapproximately fixed locations in or on modular tile to therebyfacilitate the alignment and interconnection between correspondingstandardized inter-connectors of adjacent modular tiles.
 26. The ICdevice of claim 8, in which at least one of said modular tiles furthercomprises a memory storage device.
 27. The IC device of claim 26, inwhich said memory storage device is volatile or non-volatile or acombination of volatile and/or non-volatile.
 28. The IC device of claim26, in which at least one of said modular tiles and/or memory storagedevices is/are configured to be uniquely addressable.
 29. The IC deviceof claim 26, in which at least one of said modular tiles is configuredto control an electrical and/or performance characteristic at least inpart based on its associated memory storage device.
 30. The IC device ofclaim 26, further comprising a standardized set of connectors thatcommunicatively interconnect said modular tiles, wherein at least aportion of said standardized inter-connectors comprised by each modulartile are disposed at approximately fixed locations in or on modular tileto thereby facilitate the alignment and interconnection betweencorresponding standardized inter-connectors of adjacent modular tiles.31. The IC device of claim 30, in which said IC device is configured touse the same signal lines of said standardized inter-connectors for bothaddressing said memory storage devices and transferring the data to andfrom said memory storage devices.
 32. The IC device of claim 30, inwhich at least one of said modular tiles is configured to control anelectrical and/or performance characteristic at least in part based onits associated memory storage device.
 33. The IC device of claim 8,further comprising interfacing circuitry configured into at least one ofsaid tiles, said interface circuitry being operable to properlyinterface said at least one interface configured tile to saidstandardized inter-connectors.
 34. The IC device of claim 8, in which atleast one of said modular tiles is configured to generate a voltagereference and/or clock signal(s) that are operable for use by at leastother of said modular tiles.
 35. The IC device of claim 8, in which atleast one of said exposed terminals is embedded in or with said modulartiles or a similar geometric construct.
 36. The IC device of claim 8, inwhich none of said exposed terminals are embedded in said modular tilesor a similar geometric construct.
 37. A method of constructingintegrated circuits (IC), the method comprising: Steps for defining aplurality of modular tiles or similar geometric construct suitable for aparticular end-application; generating a physical layout for the ICusing said modular tiles or similar geometric construct; generating chipdata corresponding to said modular tile IC layout; generating maskreticles corresponding to said chip data; and forming the IC on a waferbased on said mask reticles.
 38. The method of claim 37, furthercomprising Steps for embedding terminals and/or bond pads into a surfaceof at least some of said modular tiles.
 39. The method of claim 37,further comprising Step for configuring at least one of said modulartiles to have at least one programmable performance parameter.
 40. Themethod of claim 37, further comprising Steps for configuring a pluralityof said modular tiles to cooperate usefully with one another.
 41. Amodular integrated circuit (IC) device, the IC device comprising: aplurality of fixed size or approximately fixed size modular tiles orsimilar geometric construct; a standardized set of connectors thatcommunicatively interconnect said modular tiles or similar geometricconstruct, wherein at least a portion of said standardizedinter-connectors comprised by each modular tile are disposed atapproximately fixed locations in or on modular tile to therebyfacilitate the alignment and interconnection between correspondingstandardized inter-connectors of adjacent modular tiles.
 42. The ICdevice of claim 41, in which said standardized inter-connectors comprisea dedicated signal line(s), uncommitted bi-directional signal line(s),communication signal line(s), control signal line(s), and/or powersupply line(s).
 43. The IC device of claim 42, in which at least one ofsaid modular tiles is configured to selectively claim operable controlover at least one of said uncommitted bi-directional signal line(s),which uncommitted bi-directional signal line(s) is/are at least operablefor inter-tile communication, control, or power supply.
 44. The ICdevice of claim 42, further comprising interfacing circuitry configuredinto at least one of said tiles, said interface circuitry being operableto properly interface said at least one interface configured tile tosaid standardized inter-connectors.
 45. The IC device of claim 41, inwhich at least one of said modular tiles further comprises a memorystorage device.
 46. The IC device of claim 45, in which said memorystorage device is volatile or non-volatile or a combination of volatileand/or non-volatile.
 47. The IC device of claim 45, in which at leastone of said modular tiles and/or memory storage devices is/areconfigured to be uniquely addressable.
 48. The IC device of claim 45, inwhich said IC device is configured to use the same signal lines of saidstandardized inter-connectors for both addressing said memory storagedevices and transferring the data to and from said memory storagedevices.
 49. The IC device of claim 45, in which at least one of saidmodular tiles is configured to control an electrical and/or performancecharacteristic at least in part based on its associated memory storagedevice.
 50. The IC device of claim 41, in which at least one of saidmodular tiles is configured to be uniquely addressable.
 51. The ICdevice of claim 41, in which at least one of said modular tiles isconfigured to convert or regulate power.
 52. The IC device of claim 41,in which a plurality of said modular tiles are properly interconnectedto be operable for joint power conversion and/or regulation.
 53. The ICdevice of claim 41, in which at least one of said modular tiles isconfigured to generate a voltage reference and/or clock signal(s) thatare operable for use by at least other of said modular tiles.
 54. The ICdevice of claim 41, in which at least one of said modular tiles isconfigured as an inter-tile master controller unit operable forconfiguring and /or controlling said modular tiles to cooperate usefullywith one another based on a programmable parameter, said programmabilitybeing operable to reconfigure said cooperating modular tile pluralityinto a desired cooperating configuration.
 55. The IC device of claim 41,further comprising at least two modular tiles that are operable eitherseparately as two separate DC-DC converters or operable together as asingle buck-boost converter.